VHDL Program : VHDL program for 4 bit binary to gray converter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Binary_Gray is
port( a: in std_logic_vector(3 downto 0);        --Bin Input
     b: out std_logic_vector(3 downto 0));    --Gray Output
end binary_gray;

architecture behavioral of binary_gray is
begin
b(3)<= a(3);
b(2)<= a(3) xor a(2);
b(1)<= a(2) xor a(1);
b(0)<= a(1) xor a(0);
end behavioral;
Posted by makeale 01/05/2015 09:14 PM Comments
 

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