How to develop VHDL code for half adder

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Course Details

Field of Study: Electronics Engineering
Course Name: Digital Electronics
Description: How to develop VHDL code for half adder with the help of logic diagram, truth table and simulation output using Xilinx software

Half adder is a combinational digital circuit with two inputs and two outputs namely sum and carry.
Since there are two inputs, we have 2^2=4 possible combination of inputs. The output is obtained by adding the two binary inputs and the carry is the determined after each addition.

The logic diagram which is obtained by simulating the VHDL code of half adder on Xilinx software is shown below. The schematic circuit for the above diagram is shown below: The truth table and Karnaugh map of the four combination of inputs for Sum is given below.  From the truth table above, it is clear that the sum is the XOR of the two inputs.
i.e Sum <= Input1 XOR Input2; (we need this to develop the VHDL code for half adder)

The truth table and Karnaugh map of the four combination of inputs for Carry is shown below.  Hence, from the truth table above, it is also clear that the Carry is obtained by using AND gate.
i.e Carry <= Input1 AND Input2; (we need this to develop the VHDL code for half adder)

Now using the above two expressions (Sum <= Input1 XOR Input2; Carry <= Input1 AND Input2;), we can write the VHDL code of the half adder easily and is shown below.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Port ( Input1 : in STD_LOGIC;
Input2 : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC); 