How to use Xilinx® for Digital System Design

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In this post, I will show you how to use Xilinx® for Digital System Design.
Xilinx® is a software used in digital system design to simulate the behavior of the digital systems using either VHDL or Verilog programs. Full Procedures starting from creating a new project up to simulation of the output with an example is shown below.

    Main Topics

  1. How to create a new project
  2. How to add a source in to a project
  3. How to check the syntax using ISE simulator
  4. How to view your design using RTL view or Technology view
  5. How to simulate the project using Test Bench Waveform

1. How to create a new project
To show you how to create a new project using an example, I will take a simple example, AND gate.

Step 1: Open Xilinx ISE from your desktop
isestart

Step 2: Click on File and then New Project
new_project

Step 3: On the new Project wizard, enter the project name (in this example ‘AND_gate’) and ensure that Top-Level Source Type is selected as HDL and click on Next
step3

Step 4: On the Device Properties fill the followings:

  • Product Category: All
  • Family: Spartan3
  • Device: XC3S200
  • Package: FT256
  • Speed: -4
  • Top-Level Module Type: HDL (you have already selected in step 3)
  • Synthesis Tool: XST (VHDL/Verilog)
  • Simulator: ISE Simulator (VHDL/Verilog)

And verify that Enable Enhanced Design Summary is selected, then click Next
step4

Step 5: Click Next

Step 6: Click Next

Step 7: You will see the Project Summary, then click Finish.
step7

2. How to add a source in to a project
Once you have created the new project the next step is adding a source.
To add the source in to your project (in this example your project is AND_gate that I have created above) follow these steps.

Step 1: Click on Project from the menu and then click on New Source
new_source

Step 2: On the New Source Wizard click on VHDL Module, enter the file name and click Next
vhdl_module

Step 3: In this step, we will define the input and output port for our project. In our example (AND gate) A and B are inputs and Y is output as shown below and click Next.
port_name

Step 4: You will see the summary then click Finish.
finish

Step 5: Close the summary as shown below:
summary

Step 6: On the VHDL code architecture part, add Y <= A and B; (for and gate) just below begin as shown below.
edit_VHDL

3. How to check the syntax using ISE simulator
Expand Synthesize – XST and double click on Check Syntax to check the syntax of the VHDL code.
If error is there, it will tell you the number of lines and you need to correct the error and check again.
check

4. How to view your design using RTL view or Technology view
Under Synthesize – XST, double click on View RTL Schematic or View Technology Schematic to view your design.
In our example (and gate) the RTL and Technology views of AND gate are as follows:
RTL Schematic Vie
rtl_view
Technology Schematic View
tech_view

5. How to simulate the project using Test Bench Waveform
Step 1: Click on Project from the menu and then click on New Source (similar to step 1 in “How to add a source in to a project” shown above)

Step 2: Select Test Bench Waveform, enter file name and click on Next
tbw

Step 3: Click Next

Step 4: Click Finish

Step 5: Select Combinatorial and click on Finish
tbw3

Step 6: From the Source select Behavioral Simulation, set the input signals, A and B as ‘high’ and ‘low’ and save it, select the test bench waveform file name, click on Process tab and double click on Simulate Behavioral Model.
tbw4

Step 7: Click Yes if you are asked to save changes on the test bench waveform file name and finally you will see the simulation output. In this example, the simulation output for AND gate is shown below.
simulation_output

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