Introduction to VHDL

As digital systems have become more complex, detailed design of the systems at the gate and flip-flop level has become very tedious and time consuming.
For this reason, the use of hardware description languages in the digital design process continues to grow in importance.
The two most popular hardware description languages are VHDL and Verilog.
VHDL is a hardware description language that is used to describe the behavior and structure of digital systems.
VHDL stands for VHSIC Hardware Description Language.
VHSIC again stands for Very High Scale Integrated Circuit.
The development of VHDL was initiated by the American Department of Defense in the early 1980s and standardized by the IEEE in 1987 for the first time.
VHDL enables hardware modeling from the gate level to the system level.
It is now accepted as one of the most important standard languages for
specifying,
verifying,
designing of digital systems.

Historical Development of IC

• (1950’s) SSI – Small Scale Integrated Circuit (10’s of transistors)
• (1960’s) MSI – Medium Scale Integrated Circuit (100’s of transistors)
• (1970’s) LSI – Large Scale Integrated Circuit (1000’s of transistors)
• (1990’s) VLSI – Very Large Scale Integrated Circuit (millions of transistors)
• (2000’s) ULSI – Ultra Large Scale Integrated Circuit (billions of transistors)

Standardization of VHDL

• VHDL was standardized in 1987 by the IEEE (Institute of Electrical and Electronics Engineers) IEEE Std-1076-1987
• All the major tool manufacturers now support the VHDL standard.
• VHDL is now a standardized language, with the advantage that it is easy to move VHDL code between different commercial platforms (tools).
• IEEE revised the language in 1993 as IEEE 1076-1993 for describing digital hardware which has been used by industry worldwide.
• VHDL code is interchangeable among different tools.

Names (identifiers) of VHDL

• In VHDL, the designer enters text according to the syntax of the language.
• Syntax means the rules of construction, or “grammar”, of the language.
• According to the syntax of VHDL, all names
  • Should start with a letter.
  • Should contain only alpha-numeric characters and underscores and no other characters allowed. i.e. Names must ne letters (A-Z, a-z), numbers, underscores (‘_’).
  • Should not have two consecutive underscores. i.e. Adjacent underscores are not allowed
  • Should not end with underscores.
  • Can be of any length (typically maximum of 255 characters).
• All names in a given entity and architecture must be unique.

VHDL Features

• Case insensitive
• inputa, INPUTA and InputA refer to the same variable
• Comments
  • ‘–’ until end of line
  • If you want to comment multiple lines, ‘–’ need to be put at the beginning of every single line
• Statements are terminated by ‘;’
• Signal assignment is done by ‘<=’
• Variable assignment is done by ‘:=’

Next Lecture: VHDL Data Types, Arrays and Operators