Lab Experiment for Logic Gates with Xilinx® Software

Share This Topic:
  •  
  •  
  •  
  •  
  •  

Lab 1: Lab Experiment for Logic Gates with Xilinx® Software ISE simulator
Aim: To realize all the logic gates input & output using test bench waveform
Materials Required: Computer with Xilinx® software Version 8.2i
Description:
This lab experiment is done using Xilinx® software Version 8.2i ISE simulator for all logic gates: NOT, AND, OR, NOR, NAND, XOR and XNOR. The program used for this experiment is VHDL and the simulation output will be shown using Test Bench Waveform as shown at the end of this page. For this experiment, A and B are the two inputs and the outputs are:
Y_not output of NOT gate
Y_or output of OR gate
Y_and output of AND gate
Y_not output of NOT gate
Y_nor output of NOR gate
Y_nand output of NAND gate
Y_xor output of XOR gate
Y_xnor output of XNOR gate
If you are new to Xilinx® software and want to know how to use Xilinx® software for digital system design, you can read this post.

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Logic_gates is
Port ( A : in std_logic; —- First Input
B : in std_logic; —- Second Input
Y_not : out std_logic; —- output of NOT gate
Y_or : out std_logic; —- output of Or gate
Y_and : out std_logic; —- output of AND gate
Y_nor : out std_logic; —- output of NOR gate
Y_nand : out std_logic; —- output of NAND gate
Y_xor : out std_logic; —- output of XOR gate
Y_xnor : out std_logic); —- output of XNOR gate
end Logic_gates;

architecture Behavioral of Logic_gates is
begin
Y_not <= not A;
Y_or <= A or B;
Y_and <= A and B;
Y_nor <= A nor B;
Y_nand <= A nand B;
Y_xor <= A xor B;
Y_xnor <= A xnor B;
end Behavioral;

RTL Schematic View
logic_gates
logic_gates_detail

Output waveform of logic gates
logic_out

  •  
  •  
  •  
  •  
  •  

Add a Comment

Your email address will not be published. Required fields are marked *