Compilation, Simulation, and Synthesis of VHDL Code

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Description

  • Course Name: Digital Systems Design
  • Course Code: ECEL 4110
  • Chapter Title: Introduction to VHDL
  • Chapter No.: One
  • Lecture Title: Compilation, Simulation, and Synthesis of VHDL Code
  • After describing a digital system in VHDL, simulation of the VHDL code is important to verify that the VHDL code correctly implements the intended design and meets its specifications.
  • So, we first simulate the design before synthesizing it to the target technology (e.g., FPGA or custom ASIC).
  • There are three phases in the simulation of VHDL code: analysis (compilation), elaboration, and simulation.

Compilation of VHDL Code

  • Before the VHDL model of a digital system can be simulated, the VHDL code must first be compiled. The VHDL compiler, also called an analyzer, first checks the VHDL source code to see that it conforms to the syntax and semantic rules of VHDL.
  • If there is a syntax error, such as a missing semicolon, or if there is a semantic error, such as trying to add two signals of incompatible types, the compiler will output an error message.
  • The compiler also checks to see that references to libraries are correct.
  • If the VHDL code conforms to all of the rules, the compiler generates intermediate code, which can be used by a simulator or by a synthesizer.

Elaboration of VHDL Code

  • In preparation for simulation, the VHDL intermediate code must be converted to a form which can be used by the simulator. This step is referred to as elaboration.
  • During elaboration, a driver is created for each signal. Each driver holds the current value of a signal and a queue of future signal values.
  • Each time a signal is scheduled to change in the future, the new value is placed in the queue along with the time at which the change is scheduled.
  • In addition, ports are created for each instance of a component; memory storage is allocated for the required signals; the interconnections among the port signals are specified; and a mechanism is established for executing the VHDL statements in the proper sequence.
  • The resulting data structure represents the digital system being simulated.

Simulation of VHDL Code

  • The simulation process consists of an initialization phase and actual simulation.
  • The simulator accepts simulation commands, which control the simulation of the digital system and which specify the desired simulator output.
  • VHDL simulation uses what is known as discrete event simulation.
  • The passage of time is simulated in discrete steps in this method of simulation.
  • The initialization phase is used to give an initial value to the signal.
  • During simulation, the VHDL statements are executed and corresponding actions are scheduled.
  • These actions are called transactions, and the process is called scheduling a transaction.

Synthesis process of VHDL Code

  • When VHDL was originally created, simulation was the primary purpose; however, nowadays, one of the most important uses of VHDL is to synthesize or automatically create hardware from a VHDL description.
  • The synthesis software for VHDL translates the VHDL code to a circuit description that specifies the needed components and the connections between the components.

VHDL Test Benches

  • VHDL test bench is used for testing a design by simulation.
  • Simulation is the execution of a model in the software environment.
  • This is done by using Xilinx ISE VHDL simulator.
  • The test bench is used in Xilinx ISE to simulate our design by specifying the inputs into the system.
  • VHDL test bench is a piece of VHDL code or program, its purpose is to verify the functional correctness of HDL model or to verify that the behavior of our system is as expected.

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