# VHDL Data Types, Arrays and Operators [slide]

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#### Description

• Course Name: Digital Systems Design
• Course Code: ECEL 4110
• Chapter Title: Introduction to VHDL
• Chapter No.: One
• Lecture Title: VHDL Data Types, Arrays and Operators

# VHDL Data Types

1. Scalar (single valued) signal types:

Bit values: '0', '1'

Boolean values: TRUE, FALSE

Integer values: -(2147483647) to +(2147483647) i.e., -(231-1) to +(231-1)

Real floating-point number in the range -1.0E38 to +1.0E38

Character any legal VHDL character including upper- and lowercase letters, digits, special characters (each printable character must be enclosed in single quotes; e.g., ‘d’, ‘7’, ‘+’)

Time an integer with units fs, ps, ns, us, ms, sec, min, or hr

std_logic values: 'U','X','1','0','Z','W','H','L','-’

‘1’ = Logic 1

‘0’ = Logic 0

'U’ = Uninitialized. This signal hasn't been set yet.

'X’ = Unknown. Impossible to determine this value/result.

'W’ = Weak signal, can't tell if it should be 0 or 1.

'Z' = High Impedance. The signal is left open.

'H’ = Weak signal that should probably go to 1.

'L’ =  Weak signal that should probably go to 0.

'-' = don't care

1. Array data types:

Std_logic_vector (n downto 0);

bit_vector (7 downto 0); array of bits representing binary numbers

1. User-defined data types:
• Construct user-defined data types using enumeration type in which all of the values are enumerated.
• Examples:

type temperature is (high, medium, low);

signal room_temp: temperature := low;

• Users can also define and create their own data types using built-in data types.
• Examples:

type byte is array (0 to 7) of bit;

Signal data_bits: byte := “01011001”;

# VHDL Arrays

• Digital systems often use memory arrays.
• VHDL arrays can be used to specify the values to be stored in these arrays.
• Arrays in VHDL can be used while modeling the repetition.
• Arrays are collections of objects of the same type.
• Can be 1D (1 dimensional) of 2D (2 dimensional) arrays.
• There are no pre-defined 2D or 1Dx1D arrays; have to be defined by designer.
• General Format of Array definition:

# VHDL Operators

• Predefined VHDL operators can be grouped into the following classes:
• Logical operators
• Arithmetic Operators
• Relational Operators

Next Lecture: VHDL Libraries and Packages

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