VHDL Description of Variables, Signals and Constants

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  • Course Name: Digital Systems Design
  • Course Code: ECEL 4110
  • Chapter Title: Introduction to VHDL
  • Chapter No.: One
  • Lecture Title: VHDL Description of Variables, Signals and Constants

VHDL Description of Variables, Signals and Constants

  • Variables and Signals in VHDL appears to be very similar. They can both be used to hold any type of data assigned to them. The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol.
  • Signals can be considered as wires in a schematic circuit that can have a current value and future values, and that are a function of the signal assignment statements.
  • On the other hand, Variables and Constants are used to model the behavior of a circuit and are used in processes, procedures and functions, similarly as they would be in a programming language.


  • A constant can have a single value of a given type and cannot be changed during the simulation.
  • A constant is declared as follows,

constant list_of_name_of_constant: type [ := initial value] ;

where the initial value is optional.

  • Constants can be declared at the start of an architecture and can then be used anywhere within the architecture.
  • Constants declared within a process can only be used inside that specific process.

constant DELAY1: time := 4 ns;

constant DATA_BUS: integer := 16;


  • A variable can have a single value, as with a constant, but a variable can be updated using a variable assignment statement. The variable is updated without any delay as soon as the statement is executed. Variables must be declared inside a process (and are local to the process).
  • The variable declaration is as follows:

variable list_of_variable_names: type [ := initial value] ;

  • Examples:

variable CNTR_BIT: bit :=0;

variable SUM: integer range 0 to 256 :=16;

variable STS_BIT: bit_vector (7 downto 0);

  • The variable SUM, in the example above, is an integer that has a range from 0 to 256 with initial value of 16 at the start of the simulation. The third example defines a bit vector or 8 elements: STS_BIT(7), STS_BIT(6),… STS_BIT(0). A variable can be updated using a variable assignment statement such as

Variable_name := expression;

  • As soon as the expression is executed, the variable is updated without any delay.


  • Signals are declared outside the process using the following statement:

signal list_of_signal_names: type [ := initial value] ;

  • Example:

signal SUM, CARRY: std_logic;

signal CLOCK: bit;

signal VALUE: integer range 0 to 100;

  • Signals are updated when their signal assignment statement is executed, after a certain delay, as illustrated below,

SUM <= (A xor B) after 2 ns;

  • If no delay is specified, the signal will be updated after a delta delay where delta is an infinitesimal time unit used by simulator for processing the signals.
  • One can also specify multiple waveforms using multiple events as illustrated below,

signal wavefrm : std_logic;

wavefrm <= ‘0’, ‘1’ after 5ns, ‘0’ after 10ns, ‘1’ after 20 ns;

Next Lecture: VHDL Modules: Entity and Architecture


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