VHDL Libraries and Packages

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Description

  • Course Name: Digital Systems Design
  • Course Code: ECEL 4110
  • Chapter Title: Introduction to VHDL
  • Chapter No.: One
  • Lecture Title: VHDL Libraries and Packages

VHDL Libraries and Packages

  • VHDL libraries and packages are used to extend the functionality of VHDL by defining types, functions, and components.
  • In standard VHDL, some operations are valid only for certain data types.
  • The IEEE has developed standard libraries and packages to make design portability easier.
  • The original VHDL standard only defines 2-valued logic (bits and bit-vectors).
  • The package IEEE.std_logic_1164 defines a std_logic type that has nine values, including ‘0’, ‘1’, ‘X’ (unknown), and ‘Z’ (high impedance).
  • The package also defines std_logic_vectors, which are vectors of the std_logic type.
  • This standard defines logic operations and other functions for working with std_logic and std_logic_vectors, but it does not provide for arithmetic operations.

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_signed.all;

Use ieee.std_logic_unsigned.all;

  • To access functions and components from a library, you need a library statement and a use statement.
  • The statement

library IEEE;

allows your design to access all packages in the IEEE library.

  • The statement

use IEEE. std_logic_1164.all;

allows your design to use the entire std_logic_1164 package, which is found in the IEEE library.

  • Whenever a package is used in a module, the library and use statements must be placed before the entity in that module period.

Next Lecture: VHDL Description of Variables, Signals and Constants

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