VHDL Modules: Entity and Architecture

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Description

  • Course Name: Digital Systems Design
  • Course Code: ECEL 4110
  • Chapter Title: Introduction to VHDL
  • Chapter No.: One
  • Lecture Title: VHDL Modules: Entity and Architecture

VHDL Modules

  • The general structure of a VHDL module is an entity description and an architecture description.
  • The entity description declares the input and output signals, and the architecture description specifies the internal operation of the module.
  • Thus, the basic VHDL model has two parts.
    • Interface-denoted by keyword ENTITY
      • defines I/O signals for the model
    • Body-denoted by keyword ARCHITECTURE
      • describes how the model works
  • Thus, the VHDL Code Structure must contains the following three sections:
    1. LIBRARY: Definitions, constants
    2. ENTITY: Interface
    3. ARCHITECTURE: Implementation, function

VHDL Entity

  • Defines the external aspects of the system.
  • Each input or output is a port.
  • Port declarations are identified by the keyword ‘port’.
  • Declaration must specify:
    • The name (identifier)
    • The direction, defined by keywords in, out, inout
    • The information type; predefined types are available
      • BIT is predefined Boolean type with values of 0 & 1
      • INTEGER is also a predefined data type
  • The port statement has the form of
    • PORT ( signal definition clause(s) );
    • Multiple signal definitions are allowed.
    • Definitions are separated by a semicolon.
  • The entity description can be considered as the black box picture of the module being designed and its external interface (i.e., it represents the interconnections from this module to the external world, as shown in Figure above).

Syntax of the entity declaration

       entity <entity_name> is

       port( <signal_name> : <mode> <type_indication>;

...

<signal_name> : <mode> <type_indication>);

       end <entity_name>;

  • The mode of the port <mode> = in, out, inout
  • in: Component only read the signal
  • out: Component only write to the signal
  • inout: Component read or write to the signal (bidirectional signals)

VHDL Architecture

  • The VHDL model body describes how the model works.
  • Separate from interface to allow for alternate implementations.
  • The architecture body contains statements that describe the operation of the module.
  • The architecture body begins with keyword ‘architecture’, and followed by an architecture name.
  • It also identifies the associated design entity interface (entity name).
  • Two distinct parts of body
    • Declarative part –signals, constants, etc. can be defined
    • Statement part -contains operational statements

Syntax of the Architecture

         architecture <architecture_name> of <entity_name> is

<architecture_declarative_part>

          begin

<architecture_statement_part>

          end <architecture_name>;

  • NOTE: The architecture declaration part must be defined before the first begin and can consist of, for example:
    • Signal declaration
    • Component declaration
    • constant declarations

Example: Entity

  • It is the interface for communication among different modules / components and define the signal port modes (INPUT and OUTPUT) .
  • VHDL code for Entity:

Entity test is

Port( A,B,C,D: in std_logic;

E: out std_logic);

End test;

Example: Architecture

  • Define all internal variables (Declarative part)

Signal X,Y : std_logic;

  • Define functionality of the chip (Statement part)

X <= A AND B;

Y <= C AND D;

E <= X OR Y;

Final VHDL code

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

 

ENTITY TEST IS

PORT(A,B,C,D : IN STD_LOGIC;

E: OUT STD_LOGIC);

END TEST;

 

ARCHITECTURE BEHAVIOR OF TEST IS

SIGNAL X,Y : STD_LOGIC;

BEGIN

X <= A  AND B;

Y <= C  AND D;

E <= X OR Y;

END BEHAVIOR;

Next Lecture: Compilation, Simulation, and Synthesis of VHDL Code

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