Tag: VHDL code

8 to 3 Encoder VHDL code and Output waveform

VHDL Code use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( en : in STD_LOGIC; a : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0)); end encoder8_3; architecture Behavioral of encoder8_3 is begin process(en,a) begin if ( en = ‘1’) then y <= “000”; else case a is when