Tag: Xilinx

VHDL Program for 2 to 4 Decoder

Title: VHDL Program for 2 to 4 Decoder Aim: To write VHDL program and simulate the output of 2 to 4 decoder using test bench waveform Materials Required: Computer with Xilinx software Version 8.2i VHDL Code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity Decoder2_4 is port ( Enable: in STD_LOGIC; A: in STD_LOGIC_VECTOR