VHDL code for 1 to 8 demux using signal assignment statement

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To write a VHDL code for 1 to 8 demux using signal assignment statement we need the logic diagram and the truth table of 1 to 8 demux. After simulation using Xilinx software the output of the test bench waveform is shown below.

Logic Diagram
demux_dgm1_8

Truth Table
demux_tt1_8

VHDL Code
vhdl

Test bench Waveform (Output)
output

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