VHDL Program for 2 to 4 Decoder

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Title: VHDL Program for 2 to 4 Decoder
Aim: To write VHDL program and simulate the output of 2 to 4 decoder using test bench waveform
Materials Required: Computer with Xilinx software Version 8.2i

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Decoder2_4 is
port ( Enable: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (1 downto 0); — Two Bit Input for the Decoder
Y: out STD_LOGIC_VECTOR (3 downto 0)); — Four Bit Output for the Decoder
end Decoder2_4;

architecture behavioral of Decoder2_4 is
begin
process (Enable,A)
begin
if (Enable = ‘1’) then
Y <= “0000”;
else
case A is
when “00” => Y <= “0001”;
when “01” => Y <= “0010”;
when “10” => Y <= “0100”;
when “11” => Y <= “1000”;
when others => NULL;
end case;
end if;
end process;
end behavioral;

RTL Schematic View
dec2_4
dec2_4detail

Simulation Output
dec2_4op

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